This invention relates generally to Static Random Access Memory (SRAM) devices and, more particularly, to SRAM devices that utilize a loadless four transistor design.
Manufacturers are designing smaller and more power efficient integrated circuits by improving CMOS processes and reducing device dimensions. Scaling is the process of modeling the changes in electrical behavior that result from reducing the device dimensions. In constant field scaling, for example, the voltage is scaled down as the device dimensions are reduced. Maintaining proper circuit operation by maintaining the appropriate stability margin is a design concern as the voltage is decreased. Many of these integrated circuits include arrays of SRAM cells. Failure to maintain the appropriate stability margin in a SRAM cell may result in a failure to retain data in the cell, a change in the data state of the cell while reading, or in an accidental write to the cell.
SRAM cell designs have progressed from a four transistor SRAM cell illustrated in FIG. 1 and a six transistor SRAM cell illustrated in FIG. 2 to a loadless four transistor SRAM cell illustrated in FIG. 3. The four transistor SRAM cell or NMOS resistor load cell, hereinafter referred to as the 4-T SRAM cell, occupies a relatively small area, but the fabrication of the passive loads involves relatively complex steps. Additionally, the 4-T SRAM cell can inadvertently become monostable or read unstable rather than maintaining its bistable characteristics. This stability problem has caused the 4-T SRAM to lose favor in SRAM cell design during the past few years. The six transistor SRAM cell, hereinafter referred to as the 6-T SRAM cell, is relatively stable and is able to operate at lower supply voltages than the 4-T SRAM. However, the 6-T SRAM cell is approximately 30% to 40% larger than the 4-T SRAM cell, and thus more expensive.
The problems associated with the 4-T SRAM cell and the 6-T SRAM cell have led to the development of the loadless four transistor SRAM cell, hereinafter referred to as the LL4TCMOS SRAM cell. The LL4TCMOS SRAM cell comprises a pair of NMOS pull-down transistors and a pair of PMOS access transistors. The LL4TCMOS SRAM is relatively small, although it is not as small as the 4-T SRAM cell as it incorporates CMOS devices. However, the LL4TCMOS SRAM cell design suffers from data retention and unintentional write problems such as failures attributable to the effects of leakage current and to the effects of noise.
Due to the intrinsic operation of SRAM cells, there is a fundamental lower limit of voltage operation for the LL4TCMOS SRAM array that is higher than the fundamental lower limit of voltage operation for periphery logic devices in the memory circuit. For example, as process scaling occurs, the periphery may be able to operate from about 0.7V to 1.2V while maintaining appropriate stability margins. However, the LL4TCMOS SRAM array may need to operate at a higher voltage than the periphery circuits, and thus may need to operate at about 1.0V to 1.5V to maintain the appropriate stability margins over the VTN. Additionally, the LL4TCMOS SRAM array is sensitive to VCC noise at lower voltages because of the reduced write margin which is approximately the VCC of the array less the VTN (VCC(ARRAY)xe2x88x92VTN).
Therefore, there is a need in the art to provide a system and method that overcomes these problems.
The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. The present subject matter provides a regulation system and method for a memory circuit, particularly an LL4TCMOS SRAM array.
One aspect of the present invention is a memory regulation system that includes at least two distinct regulators. At least one periphery regulator provides at least one periphery voltage for the periphery of the memory circuit, and a separate array regulator provides the array voltage for the memory array of the memory circuit. The array regulator is connected to the bit lines and to a reference generator. The separate array regulator allows the regulated voltage of the array to be operated at a higher voltage than the regulated voltage for the periphery circuits. The bias reference voltage causes subthreshold current to be sourced from the complementary digit lines or bit lines and through the access transistors to offset leakage current in the LL4TCMOS SRAM cells that, if not offset, could cause the cell to fail. Additionally, the separate array regulator provides a clean power supply to the LL4TCMOS SRAM array which is particularly sensitive to noise because of the approximately 80 mV per decade subthreshold current response of the p-channel access transistors which are also the load elements. As such, the separate array regulator is beneficial even if the array regulator and the periphery regulator(s) provide the same regulated voltage. Thus, the separate array regulator provides a stable bias reference voltage.
These and other aspects, embodiments, advantages, and features will become apparent from the following description of the invention and the referenced drawings.